I like VHDL. Verilog and non-blocking vs blocking assignments can trip you up so easily. As for verbose code, you spend way more time debugging and thinking about how to structure a program than you do writing text on the screen.
I prefer Verilog but what you say is true or at least should be true if you want to end up with a good, easily debuggable result.
I like VHDL, but SystemVerilog does have some very nice features.