This is not simplified, we include the full RTL and all the building blocks required to run Linux (cache controllers, MMU, debug interface, load/store unit etc.).

We are granting an open license, which means you can see the code. CPU IP usually includes many options (i.e. parameters) that need to be set by design teams before doing any FPGA integration work (synthesis, functional simulation and verification, place and route, etc.). Setting those parameters up requires a lot of expertise which is usually accumulated over years of work in SoC design.

The blog article mentions a case where a university struggled to configure the MIPSfpga CPU because (naturally) IP can be quite complex, especially if you haven’t used it before. So we’ve actually done a lot of work to create a pre-configured, pre-validated version that is easy to use by academics (lecturers, students, etc.) for FPGAs. Of course, we also state in the press release that users can change it but they need to talk to us first to ensure that the changes they make are valid and sensible. The last thing you want is to break a CPU architecture; this will affect not just the behavior of the hardware, but also the toolchain.