The article is pretty light on the technical details about the actual processor architecture.
I think their choice of naming is unfortunate, confusion with ARM's Cortex-M3 is quite likely. Or are you supposed to pronounce this "M to the third" or something?
Update: D'oh, of course it's "M-cubed". I knew that, I blame not being a native speaker for not thinking about it. :)
I'm not sure it's an ARM..
It seems to consist of "8-bit CPU, a 52x40-bit DMEM, a 64x10-bit IMEM, a 64x10-bit IROM". Those are some seriously small memory sizes, a total of 64 instructions (the IROM holds the code) really isn't a lot to play with.
Though if the silicon process technology is as good as they claim, then scaling that up a little bit (to be on-par with conventional 8-bit micros) won't be too bad. It will be interesting to see if they can maintain the kind of leakage they're talking about with a smaller process size.
AnnArbor SmartZone funding, http://www.a2gov.org/departments/finance-admin-services/smar...
U of M test track for smart/autonomous cars, http://www.mlive.com/news/ann-arbor/index.ssf/2014/03/univer...