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Comment by TaylorAlexander | Hacker News Reader

"More interesting than 10nm, though, is the news that Intel is looking to move away from silicon FinFETs for its 7nm process. While Intel didn't provide any specifics, we strongly suspect that we're looking at the arrival of transistors based on III-V semiconductors. III-V semiconductors have higher electron mobility than silicon, which means that they can be fashioned into smaller and faster (as in higher switching speed) transistors."

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To those unfamiliar with "III-V": Think GaAs (Gallium Arsenide) and friends.

gallium arsenide (GaAs) has six times higher electron mobility than silicon, which allows faster operation... Conversely, silicon is robust, cheap, and easy to process, whereas GaAs is brittle and expensive, and insulation layers can not be created by just growing an oxide layer; GaAs is therefore used only where silicon is not sufficient.

  -- Wikipedia

Gallium Arsenide Valley doesn't have quite the same ring to it does it...

Better than "Gaas Valley", at least.

How abou Gall Arse Valley?

take this as an omen of the global shelf-life of SV.

I think it's just the extra word. "Gallium Valley" sounds pretty cool, and "Arsenide Valley" sounds like a Bob Dylan song.

That doesn't sound like good news for Intel chip prices.

In many way's Moore's Law has been a law of economics. Look at the charts in the article; Intel will at least intend to continue the drop in cost per transistor, even if the price of a mm^2 of wafer continues to go up.

Will Intel be producing its own III-Vs or will it be sourcing it from somewhere else? Who are the major producers of III-Vs?

Crystalline III-V channels can be grown epitaxially on silicon substrates, with buffer layers to grade the strain due to crystal lattice mismatch. With silicon wafers heading to 450mm diameter the economics would argue against native III-V substrates.

One advantage of native III-V substrates is they are semi-insulating (very high resistivity) so there is no need for transistor isolation wells. However, insulated substrates could be obtained on silicon by means of wafer bonding with an intermediate dielectric layer.

As they say: "Gallium Arsenide is the material of the future, and will always remain so" (1986)

That's vague. I hope it's just Intel being quiet... I was under the impression that cutting-edge chips requires deep experience and planning - Intel must know exactly what they're going to move to if they're going to have any prayer of coming out with chips on a timely basis after 10nm in 2017.

It surely has to be. The jump from silicon at a mass scale is going to have an incredibly high barrier to entry so I can only see the most entrenched players making it. It seems to me a prime opportunity for the big players to entrench their {mon|du}opoly over the industry.

I know I'd be keeping specifics as tightly controlled as possible until the last moment. It's one of those rare big jumps that really separate the players in the field.

The fact is that no one knows, not even Intel. Many hoped-for technologies have failed to pan out before. For example, the industry had placed high hopes on EUV lithography (in 2007 they hoped it would be ready by 2010), but continued problems make that technology look less and less likely today, at least for the short-term. III-V semiconductors are another major hope for the industry (a hope that's been around for decades), but now delays have pushed that from 10 nm to 7 nm. Imec has been working for over 10 years on a way of growing III-V semiconductors in tiny trenches to make it cheap enough, but until they actually ship product, no one knows if it's good enough to work.

It's a scary time for the industry, as Moore's law comes to an end.

(All that said, even if no one knows for sure what's coming next, that doesn't mean nothing will. The semiconductor industry is throwing billions of dollars and thousands of engineers at many potential solutions in parallel. Even if plan A falls through, there is always a heavily researched plan B, C, and D.)

Is this description of the difficulties of EUV lithography http://semiaccurate.com/2013/02/13/euv-moves-forward-two-ste... fairly accurate or not? It's certainly very funny.

I also note that Seymour Cray wanted to do gallium arsenide CPUs back in the late '80s: https://www.youtube.com/watch?v=xW7j2ipE2Ck .

Yes, I think it's accurate. As the article says, the #1 problem with EUV is low power output. Especially with less sensitive photoresists (another problem unmentioned), today's 30 W output is not enough to churn out 100-200 wafers per hour.

By the way, an interesting alternative to blasting drops of molten tin in vacuum is to just build a multimillion dollar synchrotron and use its x-rays for lithography in a fab. This has a whole bunch of other problems, but it's an idea that engineers are seriously considering.

Most of my knowledge comes from my friend who used to work on the problem of inspecting x-ray masks.

why the jump from 193nm light to 13.5nm light with nothing in between? Would 50nm light for instance basically be exactly as hard as 13.5nm so you just go with the smallest possible?

I'm just guessing here. Current technology uses all sorts of tricks to focus/manipulate/use 193nm light so that you can build something smaller than the size of wavelength. However many of these tricks don't work with EUV or bigger but smaller than current light because it has to be done in a vacuum. So basicly you have to go even smaller to be better.

Semiconductor manufacturing is always ripe for absurdist humor, as semiconductor manufacturing is itself absurd :)

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