Intel forges ahead to 10nm, will move away from silicon at 7nm

Yeah, I don't think 1 THz is achievable, but we can likely do substantially better than 4 Ghz, even when we can't go smaller. Then there are also gains to be made from building bigger, building in 3 dimensions, decreasing waste heat, etc. I suspect that innovation with chips will get bumpier, but likely overall maintain the pace of innovation for a couple decades more - which is all we need to get into really interesting territory re AI and other things.

When Intel say they have 52nm wire pitch, this means that they produce wires that are 26nm wide, with 26nm distance between wires. Producing wires that are thinner, or that are closer together, is unreliable.

That said, they are probably able to position those wires at a higher precision. Without being involved in the manufacturing myself, I deduce this mainly from looking at optical proximity correction[1], for example, it's clear that the final masks used for production have more detail. Another indication is the fact that different masks seem to be aligned to basically nm-level precision (otherwise, the different parts of transistors and the vertical interconnects (vias) between wiring planes would not match up properly). The photographs one sees of the final product also indicate this. This means that the location of wires could theoretically be controlled very precisely, but for a mixture of wavelength and other (chemical? surface tension?) reasons, the size of the wires cannot be made smaller reliably.

I'd be curious to know how precise this alignment really is, and I've never seen numbers for it, but it must be incredibly precise. Given that a large part of it can be done optically, this is not even that surprising, compared to some of the other magic that's going on here.

[1] http://en.wikipedia.org/wiki/Optical_proximity_correction

Ironically, modern JS frameworks are getting more and more enterprise-y.

The JVM is an insane thing, and with clever enough programmers a lot can be done on top of that.

Were those Java servers written in standard Java, though? Because it's possible to write pretty low-level code in java if you're willing to compromise on standards compliance. Non-GC'ed, direct memory access is possible, I think.

Since IVB it's been more like 0-5 percent. Intel has decided to focus on reducing power consumption and keeping performance the same, since that's much easier to do now.

Have you looked at (really) random-access memory bandwidth?

It's not really exponential if the number keeps going down on each generation.

Gallium Arsenide Valley doesn't have quite the same ring to it does it...

That doesn't sound like good news for Intel chip prices.

Will Intel be producing its own III-Vs or will it be sourcing it from somewhere else? Who are the major producers of III-Vs?

As they say: "Gallium Arsenide is the material of the future, and will always remain so" (1986)

It surely has to be. The jump from silicon at a mass scale is going to have an incredibly high barrier to entry so I can only see the most entrenched players making it. It seems to me a prime opportunity for the big players to entrench their {mon|du}opoly over the industry.

I know I'd be keeping specifics as tightly controlled as possible until the last moment. It's one of those rare big jumps that really separate the players in the field.

The fact is that no one knows, not even Intel. Many hoped-for technologies have failed to pan out before. For example, the industry had placed high hopes on EUV lithography (in 2007 they hoped it would be ready by 2010), but continued problems make that technology look less and less likely today, at least for the short-term. III-V semiconductors are another major hope for the industry (a hope that's been around for decades), but now delays have pushed that from 10 nm to 7 nm. Imec has been working for over 10 years on a way of growing III-V semiconductors in tiny trenches to make it cheap enough, but until they actually ship product, no one knows if it's good enough to work.

It's a scary time for the industry, as Moore's law comes to an end.

(All that said, even if no one knows for sure what's coming next, that doesn't mean nothing will. The semiconductor industry is throwing billions of dollars and thousands of engineers at many potential solutions in parallel. Even if plan A falls through, there is always a heavily researched plan B, C, and D.)

We fixed that problem by dropping back to under 2GHz; focusing on clock rate rather than IPC and energy efficiency was just a stupid time for Intel and the industry.

Well, that was the beginning of the breakage.

Things actually broke at 90nm. Gate leakage went up enough that most analog/RF circuits scaled their transistors back up to 130-150nm dimensions while the digital guys cashed in the density increase one last time.

65nm was the first node where static RAM cells didn't scale with the rest of the digital circuitry. RAM cells are more sensitive to leakage since they have a "writability constraint" where you have to be able to shove enough electrons from outside the cell, through a transistor, with enough oomph to change the state inside the RAM cell.

40nm was where RAM scaling really broke. Designers had to start jumping through amazing hoops to support tricks for the manufacturing guys to eke out the last jump even for standard digital circuits. Most technologies started trading off multiple gate oxide thicknesses to manage leakage current.

28nm was where everything basically went to hell. The strong form of Moore's Law (twice the transistors for same cost) broke. RAM cells are way off the scaling curve. Leakage is everywhere. Multiple gate oxide thicknesses are the rule, not the exception. Designers are jumping through tremendous hoops for manufacturing (aligning all gates in the same direction over the entire chip, for example).

Below 28nm has been a disaster, and, as pointed out, a lot of the sub-28nm stuff is more marketing than actual physical dimensions.

Lots of opportunities throughout the rest of the stack too - from novel architectures to on-chip programmable logic, the end of Moore's law puts more pressure on some really interesting innovation.

eg Rainbow[0], BORPH[1], Mill architecture[2]

[0] http://www.hindawi.com/journals/ijrc/2013/789134/

[1] http://borph.org/

[2] http://millcomputing.com/docs/