Intel at ISSCC 2015: Reaping the Benefits of 14nm and Going Beyond 10nm | Hacker News Reader

Intel at ISSCC 2015: Reaping the Benefits of 14nm and Going Beyond 10nm

anandtech.com

34 pointsDiabloD310 comments

This article proposes that the naming convention of using feature size is becoming more and more marketing and less and less connected with an actual distance. [1] Does anyone around here know what the state of the resolution of these chips' features actually is? I'm curious about the actual precision of these modern lithographic techniques. I presume at some point you get into Heisenberg's territory and things get much (differently) harder.

[1] http://spectrum.ieee.org/semiconductors/devices/the-status-o...

Here's a report of a scan of Intel's 14nm technology: http://www.chipworks.com/en/technical-competitive-analysis/r...

A good example for the problem with naming conventions is that Intel's 14nm M1 has lower pitch (i.e., lower distance between wire centres) than the 14nm technology of competitors; at least as claimed by Intel some time last years and apparently confirmed by the linked article.

One way around this problem(of different densities for transistors and wires), is a new metric that multiplies the resolution of both(lower is better). Intel's metric is 3640, Samsung is 4990.It's from [1].

So Intel has 27% area advantage over Samsung. Although of course it's very design dependent.As for cost, there are other parameters, so it's a bit harder to tell.For example, today's 28nm is cheaper than the denser 20nm because it's a simpler process.

[1]https://www.semiwiki.com/forum/content/3884-who-will-lead-10... - if i'm not mistaken samsungs's 16nm should be 14nm.

The problem largely is as it gets smaller, the distance between features have to increase otherwise electrons will happily fly through your chip because we're still using silicon, and even though we keep decreasing the voltage, there gets a point where ANY voltage is going to cause electron tunneling, and we're pretty much there.

A lot of people think 10nm is as far as it gets for our existing silicon tech, newer techs beyond that will not have the dramatic increase in performance we're used to.

> A lot of people think 10nm is as far as it gets for our existing silicon tech

I'm not really doubting this assertion, but I reckon I've heard this every 5 years about different scales, and then somebody sneezes some cobalt dust on a wafer and off we go again.

What makes the lower bound 10nm rather than, say 6 or 4nm? Or are you saying that 10nm is not a lower bound, but rather the start of a performance plateau?

An ex manager from DARPA, which was responsible for similar stuff there said he believes that 5nm is the physical limit of scaling. but making them will be more complex, hence expensive, and he think the economics could stop working before.

Also if we're talking about the economics, there really are 2 foundries(TSMC and Globalfounries/Samsung alliance) make top-end chip for others(Intel doesn't count, chip designers don't/won't trust them). Do with almost no competition - do you expect prices to go down ?

So maybe we will see further performance improvements, But no cost reductions.

> So maybe we will see further performance improvements, But no cost reductions.

Don't mean to be snarky, but how can the industry see performance improvements without cost reductions?

Assuming new process technology produces chips with equivalent performance to current models at the same cost (aka $/mm2 increases in step with performance), but allows more thermal headroom for higher performance models than current models (at additional cost), then wouldn't that be economically infeasible?

I can't imagine with massively-parallel-on-commodity-hardware for datacenter processing (correct/incorrect characterization?) there's enough aggregate demand for "more performance at higher total cost" to subsidize an entirely new process node...

>> but how can the industry see performance improvements without cost reductions?

I imagine for example, data centers willing to pay the same price for a chip that only reduces power. Or that chips that will be twice as fast but cost double, but they'll allow to double the density in the server room, etc.

BTW that's what already happening in mobile SOC - the new process nodes aren't cheaper, only lower in power.

> I imagine for example, data centers willing to pay the same price for a chip that only reduces power.

That's not valid with the original statement though.

Unless the new chip that costs the same but runs at reduced power does not have an lower-cost version that runs at the previous power.

Not seeing the logic here. If a mobile SoC of performance X and TDP Y and cost Z on the previous node, and the current node provides performance X at TDP<Y and cost Z on the current node, then you could substitute a lower performance part, running at the previous node's power envelope, and realize cost savings (e.g. performance X(OC <X -> X) at TDP Y(OC <Y -> Y) at cost <Z).

I'm not seeing the possibility of "performance improvements without cost reductions" other than at the ultra-high-end (aka "what was previously not possible").

Its a performance plateau because even if features continue shrinking (and they will), the distance between said features isn't decreasing, due to said electron tunneling effect.

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