It's memory map is a little different. (For MIPS32 at least, not sure what KSEG of MIPS64 looks like) 80000000-9FFFFFFF is fixed to a cached view of the first 512MB of physical memory. A0000000-BFFFFFFF is fixed to an uncached view. Everything else is only accessible by mapping it via the MMU (both from a physical and virtual context). Last I played with MIPS cores, they were only soft fill TLBs, but maybe that's changed. Thumb2 is more expressive than MIPS16 IMO (but that's just, like, my opinion, man).

Other than that, the microarchitectual differences between individual implementations greatly outweigh the influence of the ISA, but for an in order design at least you can probably make a MIPS that'll compete well with an ARM for less transistors.