Hacker News Reader

ARM is using L3 cache as a DMA-like interconnect, on the SoC side of things.

I'm not sure about ARMv8 but in ARMv7 SoCs the ARM Subsystem does not include L3. Plus each L1 is tied to each core.

The L3 cache is 'integrated', which I presume means it's different names for the same thing.

Ah! Thanks for sharing. It is for ARMv8 which I really need to read up on.