x86 has always been almost but not quite completely backwards-compatible in the "edge cases", ever since the 286 changed what PUSH SP put on the stack. With regards to memory ordering, x86 is already considerably much more restrictive than other architectures, although that might start to change in the future...

Trying to read this paper, what's a little annoying is that the authors don't seem to define the important acronyms and/or leave them to forward references: "SB" I assume meant "Sandy Bridge" (i.e. that was observed beginning with that microarchitecture) until a little later when I realised they were talking about store buffers, "IRIW" (is it somehow related to "IWP"?) is never defined. Also odd are the examples named "n6", "n5", and "n4b" in that order; a subtle pun about ordering?