It seems there is no synthesis (which is to be expected without vendor support). With 'limited' conversion to VHDL/Verilog, I wonder how useful this is for actual implementation.
Also from the site I couldn't find any mention of higher level functionality such as generics, etc.
For parametrizability, you have the full Python power at your disposal. This is also true for conversion, because conversion happens after elaboration of the design.
Pretty cool to see this, and going forward as a roadmap there is much they could borrow from SystemC.
OTOH, one of the nice things is the ease of moving from a numpy model of the system to RTL. And using PyPy for running simulations really makes MyHDL hum along quickly [0]