The handwavy section on RISC-V is underwhelming. Yes the ecosystem is still nascent but something like the SpacemiT K3 is far from "abysmal" for vector operations and would make a nice test case with its two core types both supporting RVV 1.0 (one with vlen 256, the other with vlen 1024). On the more industrial side, for example the SiFive Intelligence X280 has been used in TPU by Google for years already and I doubt they are the only ones so calling the ISA completely irrelevant is a bit of a stretch.

Just for the sake of curiosity it would be nice to have a peek at what SIMD in Rust looks like on RISC-V today. Yes, even if it requires some "obscure compiler flags" for now (while we wait for the Oilsm extension).