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Comment by kens | Hacker News Reader

Author here for all your core memory questions...

Please write an article about that French computer Project idea: find 64kb kb of such memory and connect it somehow into Apple2, atari and other 8bit cpus hehe

It must be possible to have some hardware adapter to map RAM into that type of memory.

Or even over serial...

ps. Related story: around 10 years ago Texas Instruments started to use FRAM in some of their 16 bit MCUs (msp430 family)

It works exactly like core memory - data still intact after power resets.

I've already written articles about the French computer and FRAM; enjoy :-) https://www.righto.com/2026/05/reverse-engineering-spacelab-... https://www.righto.com/2024/09/ramtron-ferroelectric-fram-di...

FRAM is a somewhat common retrofit for battery-backed SRAM: https://bastelblog.runlevel3.de/en/restore/ds1250-fram-repla...

No special provisions for rad hardening needed?

Core memory is very resistant to radiation. When the Shuttle computers were upgraded to semiconductor memory, radiation became an issue. The solution was to add six extra bits of storage to each word and use ECC. A background process scanned for errors and corrected them. The computer could encounter 100 bit flips per flight, so radiation was significant. (There was even an incident where a single cosmic ray flipped 14 bits.) The other problem with semiconductor memory was its volatility, so the computer had NiCd batteries for backup power to the RAM.

For details on how radiation affected the Space Shuttle's computers, see this paper: https://klabs.org/DEI/Processor/shuttle/oneill_94.pdf

On the topic of ferromagnetic computing, was there ever any serious investigation of Parametron type machines for at least parts of the flight control or other critical systems where interruptions would have been very serious?

I assume you're interested in magnetic core logic computers in general, not specifically Parametrons. In the late 1950s, NASA considered core-transistor logic for a spacecraft navigation computer due to its lower power consumption. The prototype version of the Apollo Guidance Computer (1962) used core-transistor logic. But improvements in transistors made core-transistor logic less appealing, not to mention the arrival of ICs. At the end of 1962, NASA decided to use ICs for the Apollo Guidance Computer and abandoned core-transistor logic. The updated AGC kept the core memory and core rope ROM of the earlier AGC, though.

Yes, those engineering discussions must have been interesting. By that point people had a fair amount of experience in Earth orbit but between the relative newness of space and the relative newness of computers there must have been significant new engineering. Maybe the ICBM programs had some lessons.

The Polaris ballistic missile computer, developed at the MIT Instrumentation Laboratory, was the predecessor to the Apollo Guidance Computer. It used germanium transistors along with magnetic core shift registers for memory. The Polaris computer used discrete three-input NOR gates, while the AGC used three-input NOR gates on integrated circuits. The book "Journey to the Moon" by Eldon Hall, creator of the AGC, has lots of details.

Can I confess I've never quite wrapped my head around the application of the 'inhibit' line in this?

If a write cycle is just a read cycle with a) a reversed polarity and b) you don't care about the contents of the sense line - I don't get why current coincidence is sufficient during the read cycle, but not during the write cycle?

Every description of this I've ever read, sound like inhibit and current coincidence solve the same problem - but have never left me clear on why we need to solve it twice.

The current coincidence is used to select a specific bit / core. Except it selects the same bit in every bank.

Bytes or larger words are made by stacking multiple banks together (18 in the articles case) All 18 bits would be driven in parallel by the driver over the X/Y wires to produce a coherent 18 bit value at the same moment.

The inhibit bit was so you could select which of those 18 bits (in separate banks) would be switched back to a 1, not selecting which bit across the entire bank.

ahh - I see where my dots weren't connecting, then.

I pictured having a current driver on each plane, so the data bits coming in would be enable bits for the current drivers. Which obviously means 18xQty current drivers.

I think you're describing having one big current driver for the whole job, and then data bits drive the inhibits to counter them.

I guess I'm looking through too modern a lens - pumping 18*600mA into the write cycle, plus (up to 18)*600mA into the inhibit, sounds insane to me (hitting 20A for a write) - but I can see that multiplying the current drivers may have sounded nuts in the 50s.

There are different ways of implementing core memory. The "traditional" way uses the inhibit line. The module I examined uses a "2½D" approach, which is what you originally pictured: separate current drivers for each bit and no inhibit line.

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