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This is about the hard macros in Altera Cyclone V FPGA.

I suspect the issue is in how Altera configured the IP. They may simply have disabled some part to save on area.

In the equivalent AMD/Xilinx parts (Zynq), you connect up all the hard IP macros using the FPGA fabric.

If the hard cores are configured with incorrect cache coherency options you may not be able to correct the issue in fpga fabric.

But this is pure speculation, I haven't checked Cyclone V documentation myself.