Hacker News Reader

Indeed, this is a problem for an energetic student who has free access to every tool in the Cadence, Synopsys, and Mentor portfolios: take the GDS-II layout, run it through extraction, generate a netlist, convert to higher-level blocks ("netlist-to-gate recovery"), translate to RTL HDL, then attempt to work out "what it does."

This is just a job posting in disguise for Jane Street: solve the puzzle, get a call from one of their recruiters.

Nope. I work at Cadence and literally have free access to every one of our tools, but I didn't use a single one of them to solve the puzzle.

The Last Starfighter :).

No need for Calibre. Me + KLayout + Claude had a verilog sim of the example vcd input and gate-level netlist 30 minutes after I cloned the repo.

It's even easier in this case because they've included the original verilog source ....

No, that's for the warmup. The real puzzle only has a .gds file available.