The 32-bit Arm architectures have used several kinds of floating-point units, with very distinct capabilities, so when compiling a program for 32-bit Arm CPUs you must always provide a specific FPU selecting option to the C/C++ compiler, the one correct for the target CPU, otherwise the performance will be suboptimal. (an example of how such a compiler option looks like: "-mfpu=fpv5-d16")
Only the 64-bit Aarch64 has cleaned up this mess, so for Armv8-A there is a well defined FPU instruction set, supported by all CPUs.
The Armv9.0-A and Armv9.2-A CPUs continue to support the original 64-bit FP instruction set, but they add SVE and SVE2.
The Armv9.3-A CPUs, launched last autumn, continue to support the original 64-bit FP instruction set + SVE + SVE2, but they add SME and SME2.
The Apple CPUs implement the original 64-bit FP instruction set but they do not implement SVE/SVE2 (except in a non-performant "streaming" mode), but in the past they had a non-documented AMX extension and now they have SME.