The really intriguing part is the "Custom ADC" here, seems like some kind of 1-bit ΣΔ oversampling ADC (704 MSPS?). Single differential transistor, and captured by FPGAs LVDS RX.

Neat way to reduce cost and pin-count? But I think the typical FPGA clock tree has poor jitter performance. Not using the internal PLL(s) might help with spurs but the clock buffers are unavoidable.

The documentation mentions it's likely further degraded by noise from switching regulators. Oh the joys of hunting RF noise sources.