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Comment by pseudohadamard | Hacker News Reader

Current state-of-the-art rad-hard CPUs are made by AMD, Intel, and IBM, among others. Their server-grade CPUs have so much error resilience and protection in them that they would have been export-controlled rad-hard devices twenty to thirty years ago.

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To my knowledge neither AMD nor Intel ship any processors that are rad hard or rad tolerant. For aerospace applications this is a very specific type of device which requires specific engineering work to achieve. You don't just get rad tolerant design through standard error correction and you definitely don't get rad hard without designing for it.

AMD Versal XQR chips are RAD tolerant, at least according to the marketing material. See https://www.amd.com/en/products/adaptive-socs-and-fpgas/vers... and https://www.amd.com/content/dam/amd/en/documents/solutions/a... ("The space-grade (XQR) AMD Versal adaptive SoCs continue the AMD tradition of full radiation tolerant"). These are SoCs built around ARM Cortex-A72 and -A78 cores manufactured using modern 7nm processes.

Yes, the Xilinx space grade devices are engineered and qualified for radiation tolerance. These are FPGA socs and share no heritage with AMD desktop and server processors.

They're not advertised as such but they are. I don't have any current evals to hand but a 25-year-old paper that looked at things like the PIII concluded that "Intel processors verge on radiation-hardened devices" and another more recent one that "No apparent device degradation was apparent on any of the samples. Cumulative dose levels for exposures ranged from 1 to 17 Mrad(Si). For comparison, the ITAR level is 500 krad(Si). As noted, total dose and DR device tolerances exceed the ITAR limits for this [AMD A4-3300, 2011 vintage budget desktop CPU] off-shore fabricated design. To the best of the authors’ knowledge, AMD has not intentionally radiation hardened the device for these environments, but the technology itself supports these characteristics". IBM and Sparc CPUs are the same, tested under proton or neutron bombardment, but they don't publish dose rate figures, just FIT or MTTU.

Modern process nodes with smaller feature sizes are likely to fare far worse under radiation than the nodes of 25 years ago.

Additionally, total dose is only one part of the equation. Single Event Effects (SEE) also must be mitigated.

You can read NASA JPL's ASIC design guidance for a brief intro.

https://parts.jpl.nasa.gov/asic/Sect.3.4.html#A0

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