Sandia National Labs SA3000 8085 CPU
cpushack.com
cpushack.com
Even more interesting that they both use the IBM POWER architecture!
0, https://www.moog.com/products/avionics/spacecraft-avionics/b...
1, https://en.wikipedia.org/wiki/RAD5500
2, https://web.archive.org/web/20190226111129/https://www.baesy...
Frontgrade also advertises a rad-hard RISC-V, as does Microchip (a PIC64 variant), that I know nothing about, but seems like an inevitable next step. Seems like you could grab some Xilinx rad-hard FPGA and bobs your uncle.
In comparison radtherapy patients get 20 gray in 1-2 weeks so it's the 20/10000 = 0.02% of what these designs target
A whole body exposure of 5Gy would kill you, although it would happen over two weeks.
10kGy? Spectacularly fatal.
Additionally, total dose is only one part of the equation. Single Event Effects (SEE) also must be mitigated.
You can read NASA JPL's ASIC design guidance for a brief intro.
We need more of this kind of thing, generally: government agencies building up in-house technical capability, instead of outsourcing everything to contractors.
For instance: there should be a government-controlled pharmaceutical manufacturer of last resort. The clear benefits would be to provide extra capacity and prevent things like Martin Shkreli's scams with Retrophin/Turing Pharmaceuticals (https://en.wikipedia.org/wiki/Martin_Shkreli#Thiola_price_hi...).
But then how will politicians favor their campaign donors?
My dad worked for one for decades - the MITRE corporation, which is a nonprofit, and interestingly enough got the first .org domain. They also run CVE, and do a variety of R&D and legacy systems work, most notably air traffic control. They also entered vehicles in the DARPA challenges in the aughts, though did not do well.
And I guess when I said "government agencies" I was being too specific. What I really mean is government should build up government-controlled technical capability, which could be "weird quasi governmental entities," state-owned businesses, government agencies themselves, or some combination. Pretty much anything, just as long as it's not a privately-owned business entity.
“The chips were made on a n-on-n+ epitaxial substrate to provide latchup control, extensive guard rings around transistors were used and hardened oxides”
"Substrate" here refers to the silicon wafer on which the integrated circuits are made, which at the end of the manufacturing process is cut into individual chips, which are then packaged as CPUs in this case.
An epitaxial wafer is a wafer on which epitaxial growth has been done before the rest of the manufacturing process. The wafers are cut from a huge crystal that has been grown from molten silicon. Initially they have a uniform concentration of doping impurities throughout their volume.
Epitaxial growth means that an extra layer of silicon is grown on the wafer and the growth is done in such a manner that all the layer is a single crystal and its lattice continues the crystal of the wafer, without interface defects.
The purpose is to have a different concentration of impurities in the extra layer, compared with the base wafer. N-on-n+ means that the initial wafer contained N-doping impurities, e.g. antimony, in a very high concentration (+), so that its electrical resistance would be minimum, while the "n" epitaxial layer also contains an N-doping impurity, e.g. phosphorus, but in a much lower concentration, so that it has a high electrical resistivity.
Both the fabrication of silicon wafers and the epitaxial growth are typically done by other companies than those that make integrated circuits, so the IC maker, or a silicon foundry like TSMC, buys epitaxial wafers according to a certain specification and they use them as the starting material in their manufacturing process.
"Latchup control" is a term specific to CMOS integrated circuits. In CMOS there exists a parasitic thyristor (a.k.a. SCR) composed of 2 parasitic bipolar transistors. If the parasitic thyristor turns on, it applies a short-circuit on the power supply, causing a huge electrical current spike, which normally destroys the integrated circuit, perhaps also other things if the power supply is not protected against short circuits.
In order to prevent the latchup of the parasitic thyristor, the structure is modified in various ways to reduce the gain of the parasitic transistors. If the gain is low enough, the thyristor cannot turn on.
Using a simple n substrate (which is cheaper) results in a high gain for the parasitic pnp bipolar transistor. Using an epitaxial n-on-n+ wafer reduces the gain of the pnp, lowering the probability of latchup.
Guard rings around transistors (which are made by diffusing certain doping impurities and then possibly also covering the diffused ring with a polysilicon or metal ring) have various purposes, typically related to preventing the electrical breakdown of the transistors at lower voltages than intended. This is especially important for radiation-hardened devices, because the most frequent effect of the passage of a ionizing particle through the semiconductor would be to generate mobile charge carriers that could cause the electrical breakdown of a transistor.
"Hardened oxide" is a more ambiguous term, but I assume that here it refers to high-quality oxide, i.e. which has a high value for the electrical field that can be sustained without electrical breakdown.
[1] yes...I know the TRS-80 had a z80, not an 8085. Close enough.
The inertial navigation system is the very crazy part, along with the nuclear fusion warhead design itself.
https://thebulletin.org/2017/03/how-us-nuclear-force-moderni...
What, so that they can debug in Chrome and put the fusing and inertial navigation processes in isolated web views?
The rate at which an object in the physical world can alter its trajectory is ultimately limited by the strength of molecular bonds in the material it is made from. Exceed that limit and the object will disintegrate. This upper bound is extremely slow from the perspective of a CPU, making it computationally trivial. A computer can react orders of magnitude faster than the quickest physical objects.
I would also imagine that there could be processing necessary that is mostly unrelated to manoeuvering speed (inlet/control surface management, etc). Perhaps some hypersonic experts could weigh in and let us know :)
Real materials are considerably worse than theoretical and you also have to optimize for other properties. The classified part is often more about the processes for fabricating specific materials. This can be extremely non-obvious and difficult.
All the exposed surfaces of a hypersonic missile are themselves limited by material physics. A major problem in hypersonic research was material surfaces degrading so quickly that they lose precision of control. The CPU can send commands but the physical materials of the guidance system don't respond in a reliable way due to the material degradation.
Fun problems.
Even without the layers & cruft though, the raw perf is astounding to those of us who remember 8 bit 1Mhz microprocessors. Today’s gamers are used to double-digit teraflops(!) of compute, just to render all the pixels for Minecraft or Fortnite.
I don’t know if there’s a better way these days, but for me Arduino has been an easy & super fun way to futz with a tiny bare metal microprocessor.
Not a programmer by trade, I prefer hardware...had no idea until recently how valuable the training was. We learned BASIC and 8085 machine code as well as building logic circuits from discrete parts. Then I used basically no code myself for 15 years until I learned Arduino. Knowing the basics certainly helped me know what was going on. From there it was just syntax for languages.
Clearly you meant the TRS-80 Model 100.
> An 8085 processor that could handle 1×106 rads of radiation with only a 25% reduction in performance, and 3×106 rads with a 40% drop.
Hmm, from where did they copy-paste this mangled scientific notation?
Ah here we are, pg. 37 (46 in PDF file): https://apps.dtic.mil/sti/tr/pdf/ADA063902.pdf
I guessed after about a second of thought that this actually meant 10^6. If I had to guess how this happened, somebody just wrote their prose in Word with the 6 in superscript and cut and paste it into HTML which lost the formatting.
I think it's a shame if you consider the whole article (which I personally found very interesting) as slop because of 2 incorrectly formatted numbers that could easily result from a cut-and-paste error. It's clear the article hadn't been well proof read as there are a number of spelling mistakes too, but that doesn't make the content itself slop.
The only overlap from the document with the text you quote is the "106", which is a pretty common mis-formatting issue.
I seriously doubt you need to fabricate 50k CPUs for a single space probe, including backups, testing chips, etc.
Back then an interface between terrestrial computer systems and a Zeta Reticulan spacecraft required a small supercomputer on our side.
At least not from a practical perspective.
From an economic perspective, stopping after a single small run is just wasteful. The upfront design costs are so high, and the per wafer costs are so slow that you might as well make a lot extra. Maybe you can find a use for them, or sell them to someone else.
I read they had their own fab, so the minimum production run aspect would appear moot.
The customer would order this minimum quantity, and most of it will probably be kept as spares.