In single threaded code, the unused cores can be powered off.
Another interesting note from that talk was that they had spent a large amount of time making an 8 socket architecture with quick-connect paths between all pairs of sockets for memory transport. Unfortunately that was not as important as believed either, since the programs that typically benefit from 8 CPUs normally have good memory properties anyway.
Not sure if either data-points are true, but interesting nonetheless.
Think about how much larger a CPU would have to be to include an entire gigabyte of cache, much less multiple gigabytes.
Second, DRAM is made differently from CPUs, and it is difficult to use two different processes on the same silicon.
Third, squeezing 4GB of DRAM onto a single CPU die? How?