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The terms to search for are fan-out wafer level packaging (FOWLP) and TSMC InFO. The chiplets come from different wafers and are reconstituted into a molded plastic wafer, allowing multiple die side-by-side. Then multiple layers of wires are built on top, terminating in a BGA.

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Ok, part of my confusion was that it was being presented in contrast to InFO-oS and InFO-PoP, but it appears to mostly be a modified version of InFO-PoP called InFO-M? Because Apple has been using InFO-PoP for almost a decade at this point, starting with the A10.

Apple has not shipped an InFO-PoP with side-by-side integrated die yet. This is expected to be the first one, using RDLs for the die-to-die interconnect (so different than M-Ultra series that uses silicon bridges).

My astonishment at these manufacturing processes is never-ending.

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