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Comment by lance_ewing | Hacker News Reader

I'm also using the knowledge gained from reverse engineering the VIC chip to contribute to a soon to be released VIC chip replacement device called the PIVIC, powered internally by a Pico 2 chip.

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Sounds cool! Similar to the SID project, assuming you're also aiming for pin compatibility.

I'm curious why you choose the pico platform over something like TinyFPGA which could be near 100% gate level compatible over a pico with software emulation. I bet the < $3 ICE40 has enough gates?

I haven't really looked at the pico2 yet, maybe it's one of those new hybrid arm+fpga designs and you'd have the best of both worlds?

EDIT: sadly no CPLD/FPGA on the pico2 front, at least according to [1]. Pico2 does add a new RISC-5 core (as a coprocessor? I only skimmed...) So I guess you'd have to do a bunch of timer interrupts to keep things in your emulator clock aligned if you're going pin compatible.

1. https://pip-assets.raspberrypi.com/categories/1214-rp2350/do...

For a couple of reasons: The first is that there are already a couple of projects using FPGA to create a VIC chip replacement, e.g. Victor by Jon Brawn, and FATVIC by Thomas Lövskog. The main trigger to try a Pico 2 version was when I saw sodiumlightbaby's OCULA project for the Oric. The ULA in the Oric is the equivalent of the VIC chip in the VIC 20, i.e. the main custom chip. When it dawned on me that he was using the Pico 2 for the OCULA, I thought, "Hey! Why not try the same thing for the VIC chip?". So we've been collabing on it over the past 12 months. I think you're right though, that devices like the Victor that use FPGA will be able to get closer to 100% compatibility. The PIVIC will be an alternative that might not be 100% compatible but is very close and would suffice for most.

Yeah, the PIVIC is pin compatible, and the same size as the original chip, so no overhanging bits. The PCB is as big as the original VIC chip.

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