> Sure, now define "total". Which accesses does that affect and which ones does it not? Is device memory included? PCIe memory? Are there ordering guarantees between mappings with different permissions?

At a basic level TSO is a model for how cores interact and devices are weird, so I'd say those get to be unspecified.

And ideally you want a line saying if the instruction cache needs to be flushed for self-modifying code since that's kind of a violation if not specified but it's a forgivable one.

> Then, define "store ordering".

Sure, though I'm not promising my wording is perfect: In TSO, when stores complete they become visible to all other cores and all cores agree on the exact same list of completed stores.

> Does it affect loads in any way? Or simply just stores?

Depends on what you mean by "affects". Loads in one core might not see stores from another core that have not yet reached the global/total list.