It does, yes. But the DDR RAM available on the target board is DDR3 which is actually quite inconvenient for retro projects for a number of reasons.

Quite apart from the increased complexity, the most important difference is that there's a minimum speed as well as a maximum speed for modern DDR RAM, which means there's usually quite a narrow window of achievable clock rates when getting an FPGA to talk to DDR3.

I suspect that's why the author chose to use the DDR for video: It's usually easy to keep plain old SDRAM in lockstep with a soft-CPU, since you can run it at anything between 133MHz (sometimes even more) and walking pace, so there's no need to deal with messy-and-latency-inducing clock domain crossing.

Streaming video data in bursts into a dual-clock FIFO and consuming it on the pixel clock is a much more natural fit.