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Comment by bgnn | Hacker News Reader

If you are running engineering jobs (HPC) like electrical simulation for chip design the only two thingd you care about are the CPU clock speed and memory RW speed.

It's unfortunate that we can only have 16 core CPUs running at 5+ GHz. I would have loved to have a 32 or 64 core Ryzen 9. The software we use charge per core used, so 30% less performance is that much extra cost, which is easily an order of magnitude higher than a flagship server CPU. These licenses cost millions per year for couple 16 core seats.

So, at the end, CPU speed is determining how fast abd economically chips are developed.

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>These licenses cost millions per year for couple 16 core seats

The ROI on hiring a professional overclocker to build, tune and test a workstation is probably at least break even. As long as the right checksums are in place, extreme OC is just a business writeoff.

I had a conversation like this with a business that had been around for decades and suddenly grew 100x because some market they were in “took off”. They had built up decades of integration with a legacy database that was single threaded and hence they couldn’t scale it.

Given the urgency and the kind of money involved, I offered to set up a gaming PC for them using phase change cooling. Sadly they just made the staff work longer hours to catch up with the paperwork.

That’s pretty common in the HFT realm already.

https://blackcoretech.com/

I'm in disbelief that the software you run is completely insensitive to IPC and instruction latency. Without those number, clock speed is meaningless.

I don't have those numbers, but here is AMD's on results on Cadence Spectre X with different gen EPYC CPUs, maybe this helps for you to understand the issue: https://www.amd.com/content/dam/amd/en/documents/epyc-techni...

About the technical problem: it's ODE solution for a sparse matrix of 10s of millions elements. Sparsity comes from the locality of interactions within a chip: not every transistor is connected to thd others. So the modern simulators make use of this sparsity to divide the circuit to independent chunks and spread over to multiple independent threads.

Scale of the compute time is not objective, but typically anywhere from couple hours to couple of months. Most top level chip integration verification jobs take weeks. Because of this we spend months for verification after the design is pretty much finish before the tapeout. This applies for every single reasonably complex chip.

Threadripper can OC to 5+ GHz.

I'm waiting to get my hamds on Threadripper Pro 9995WX, which is Turbo at 5.4GHz. Currently I'm using Ryzen™ 9 9950X, Turbo at 5.7 GHz. It's a 7% difference.

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