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Comment by MutedEstate45 | Hacker News Reader

[flagged]

It appears that your entire profile is simply LLM generated comments, including this comment right here. Please do not do this on HN.

The parent comment absolutely has the LLM stench.

Appears? How so?

> If you've ever been burned by Verilog's "works in sim, breaks in synthesis" gotchas

This is LLM phrasing. It's trying to be witty and relatable about an experience basically no person has ever had - or at least, those people being hardware engineers, they usually don't try to be witty and relatable in forum comments.

I don't know though, the comment as a whole doesn't feel AI-generated, but maybe AI-assisted.

Apart from the telltale direct paraphrasing of the Amaranth home page, the discourse about "works in sim, breaks in synthesis" can be regurgitated from any mildly disappointed essay about Verilog and feels plausibly AI-generated to me.

"The result: a design that passes simulation is far more likely to synthesize identically, averting costly back-end surprises"

This is the sort of phrasing that either a committee of marketing people wrote up, or an LLM.

It's been a while since I've done this stuff, but VHDL seemed like this to me: that generally if it compiles, it synthesises. I really battled with Verilog!

But what is it for? It would be impressive if they used this to develop their gravitons but I find that hard to believe. What's the use case?

https://glasgow-embedded.org/

Which uses a single Python codebase to implement both the gateware (as Amaranth) and the software which interacts with it.

https://greatscottgadgets.com/cynthion/ is another in-production user of it, a USB protocol analyzer and tool.

Amaranth is basically SystemC but in Python (and it's much easier to use and works better)

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