I don't think any mathematical relationship between the address bus and either 640KiB or 640MiB was intended, it was just the anchor point for how huge 4GiB of addressing was viewed at the time.
The article then goes on to say that the NV1 used 23 bits of the address bus but adds in the next paragraph that 16 bits remained to use for data. That math isn't working out for me.
Actually, I'm really struggling to understand how this scheme would work at all. It strongly implies open addressing with no other MMIO devices to conflict with, but that's just not how I thought PCI worked. Maybe someone who knows more can explain it to me.