When debugging/fixing timing problems, or trying to implement a functional change using only metal layers - yes, it is absolutely still necessary to debug verilog at the gate level.

Also, "just a tooling issue" is a pretty big problem when you're talking about something that wants to be adopted as part of the toolchain.

I do for the most sensitive path of the design, but only because it's needed. I don't want to have to look at it for day-to-day debugging, where it's just a distraction.

> just a tooling issue

The word "just" is carrying the weight of the world on its shoulders…

> it's just a tooling issue

FPGA toolchains are infamous for one of the worst and cursed toolchains in the world. Where writing tcl scripts to imperatively connects blocks together in a block diagram that will integrate all the verilog code is not just normal, but encouraged. Because their internal block diagram description file is git hostile