If the output SystemVerilog is unreadable I'm unlikely to use this. SV is still the lingua franca for physical tools. I'm not debugging timing on something that looks like this:

    localparam[14:0] _e_953 = 0;
    localparam[14:0] _e_958 = 1;
    assign _e_956 = \count  + _e_958;
    assign _e_955 = _e_956[14:0];
    assign _e_948 = _e_949 ? _e_953 : _e_955;