Comment by westurner | Hacker News Reader

Comment by westurner | Hacker News Reader

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> Specifically, the researchers operate a transistor under what are called "punch-through conditions." This happens when charges build up in a semiconductor in a way that can allow bursts of current to cross through the transistor even when it's in the off state. Normally, this is considered a problem, so processors are made so that this doesn't occur. But the researchers recognized that a punch-through event would look a lot like the spike of a neuron's activity.

> The team found that, when set up to operate on the verge of punch-through mode, it was possible to use the gate voltage to control the charge build-up in the silicon, either shutting the device down or enabling the spikes of activity that mimic neurons. Adjustments to this voltage could allow different frequencies of spiking. Those adjustments could be made using spikes as well, essentially allowing spiking activity

> [...] All of this simply required standard transistors made with CMOS processes, so this is something that could potentially be put into practice fairly quickly.

ScholarlyArticle: "Synaptic and neural behaviours in a standard silicon transistor" (2025) https://www.nature.com/articles/s41586-025-08742-4

How do these compare to memristors?

Memristors: https://en.wikipedia.org/wiki/Memristor

From "A Chip Has Broken the Critical Barrier That Could Ultimately Begin the Singularity" (2025) https://www.aol.com/chip-broken-critical-barrier-could-17000... :

> Here we report an analogue computing platform based on a selector-less analogue memristor array. We use interfacial-type titanium oxide memristors with a gradual oxygen distribution that exhibit high reliability, high linearity, forming-free attribute and self-rectification. Our platform — which consists of a selector-less (one-memristor) 1 K (32 × 32) crossbar array, peripheral circuitry and digital controller — can run AI algorithms in the analogue domain by self-calibration without compensation operations or pretraining.

Can't these components model spreading activation?

Spreading activation: https://en.wikipedia.org/wiki/Spreading_activation

Memristor is cool, and it is all in one (including memory), but it is not standard CMOS process.

That is whole difference.

Any way, will be sort of CCD matrix to use any of these techs (may be something like modern Flash as storage, or DRAM cell with refresh), but CMOS is very straightforward to produce and to use.

Why I mention CCD - it is analog storage with multiple levels, organized as multiple lines with output line on one side. It could also be used as solid-state circular buffer to access separate cells.

So, these CMOS transistors will work as neuron, but weights will be stored as analog value in CCD.

Is that more debuggable?

Re: the Von Neumann bottleneck, debuggability, and I guess any form of computation in RAM; https://news.ycombinator.com/item?id=42312971

It seems like memristors have been n years away for quite awhile now; maybe like QC.

Wonder if these would work for spiking neural behavior with electronic transistors:

"Breakthrough in avalanche-based amorphization reduces data storage energy 1e-9" (2024) https://news.ycombinator.com/item?id=42318944

Cerebras WSE is probably the fastest RAM bus, though it's not really a bus it's just addressed multiple chips on the same wafer FWIU.

> Is that more debuggable?

I've seen many approaches to computing in my life - optical, mechanical, hydro, even pneumatic. Classic digital based on CMOS is the most universal with huge range of mature debugging instruments.

CMOS digital is so universal, it even worth to pay magnitudes worse power consumption before find best structure, and then, sure use something less debuggable, but with better consumption.

Unfortunately, I don't have enough data to state, which will be better on power, CMOS or memristor. Just now CMOS is mature COTS tech, but memristor is still few years from COTS.

Cerebras, as I know, based on digital CMOS. Just using some tricks to handle near whole wafer space. BTW, Sir Clive Sinclair tried similar approach to make wafer-scale storage, but unsuccessful.

> it's not really a bus it's just addressed multiple chips on the same wafer

I'm electronics engineer, and even have once baked one chip layer on semiconductor practice, so I'm aware about technologies.

As I said before on Sinclair, few companies tried to make new on semiconductor market, and even some have success.

RAM manufacturers for a long time using approach of make multi-chip on one wafer - most RAM chips actually have 4..6 RAMs in one package, but few of them don't pass tests and disabled by fuses, so appear chips with 2 or 4 RAMs enabled and even with odd number of enabled chips.

Looks like Cerebras use similar to RAM manufacturers approach, just for other niche.

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