Most of the advanced chips (the 16 nm that Xilinx uses for UltraScale/+ and below) are flip-chip wafers and have an interposer which is basically a very dense PCB that helps fanning out the extremely dense and small pitch of flip-chip bumps. They will usually include extra low impedance ("landscape" orientation) capacitors on the substrate, which leads to much relaxed PCB decoupling requirements.

Having designed FPGA boards with both their 7th generation parts and their Zynq UltraScale parts, the internal capacitors are such a time and cost saver in terms of being able to fan out more signals without more PCB layers

I can also attest that even relatively "slow" chips like 14 nm FinFET MPUs from Renesas have decoupling caps on the substrate