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Comment by crote | Hacker News Reader

By that logic any OSHW project using integrated circuits is closed-source. After all, the PDK is proprietary, the fab's production pipeline isn't publicly available, and there isn't even a way to confirm the HDL supplied is actually what is being used in the chip!

If we want truly open-source hardware we'll have to go back to relay computers. Everything beyond that is "a joke".

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No love for a verilog design in an fpga as open source hardware?

It’s a flawed surrogate of course - lower performance and higher cost than an asic produced at volume - but the open source hardware aspect is very strong.

The circuitry (ie transistor level) of the FPGA is still closed no?

Yes, but there are many different fpga’s, many of which many verilog will run on, which to my mind makes the downsides of proprietyness low enough that this might be the sweet spot to stop at going down the stack..

however awesome an open source fabbed asic or fpga would be of course.

It's not open unless you can make it from sand.

Actually, it's not open unless you can make it from hydrogen atoms.

That’s going too far. RYF certification is what you could reasonably require.

> By that logic any OSHW project using integrated circuits is closed-source.

There are degrees to things. It's not cool to try to claim the prestige of "open source" when the entire board is nothing but a vehicle for your very-much-closed processor design.

> when the entire board is nothing but a vehicle

You can get the board design and order it manufactured yourself, or you can change it to suit a different processor that's more open.

What about the many real open source RISC V?

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