Note that it's only on one 1.6GHz core, and still pretty anemic otherwise (pi form factor, it's to be expected.) So something "deskop grade" with all the nice extensions and other goodies is probably still a ways off. Maybe next year; we'll have to see -- but lots of useful extensions continue to be ratified today, so it may still be a while before things "cool off."
Arm A53 (Pi 3, October 2012 - February 2016), A72 (Pi 4, Feb 2015 - June 2019), and A76 (Pi 5, May 2018 - September 2023, or January 2022 for Radxa Rock 5B) all took longer.
P670 was only announced in November 2022. If a board ships by the end of 2025 it will be doing very well.
Traditionally in x86 Intel and AMD do all the first three steps in one company, with the stages overlapped, and feedback.
Also, Intel and AMD (and even more so Apple) don't announce a new chip until it is very close to shipping. They might have been working on it internally for five years before that.
Arm and RISC-V companies have to make public announcements when a core is nearing design completion, to give a chance for companies such as Allwinner and Rockchip and Broadcom and Mediatek and Sophgo and Starfive to take a look at the specs and decide that it might be interesting to build a chip using that core.
> I know the round trip time from the foundries is ~3 months.
That's only if the chip works first time. Many don't and need several re-spins. I believe 3 or 4 is not uncommon. And variable amounts of re-design and re-layout and re-verify time between each of those ~3 months at the foundry.
Given that, it would be a brave company that went straight to mass-production without a round of test chips first, so you've got 2x ~3 months, plus "bring up" time in between, even in the best case.
I is the base integer instructions
M is integer multiplication
A is atomic
F is single precision float
D is double precision
G is shorthand for all of the above + 2 others that I honestly have no idea what they do
The original RV32I and RV64I required some control registers for high frequency counters and instruction counters. You also needed the instructions to access these registers. This proved to be too complex for the simplest implementations, so recently (five years ago?) this functionality has been moved to their own extensions.
Including these extensions in G makes the current G have the same functionality as the original G.
i.e. features have not been removed after ratification.
CSR (i.e. status) register and instruction fence extensions. Instruction fences are most useful in cases where you modify text section during runtime (e.g. JIT or code hot reload) such that you need to ensure the consistency of code across different harts