What does 'layer' mean in this context? I'm only familiar with planar style logic process nodes which have maybe up to 20 layers (and way more lithography steps to manufacture those layers), but I am completely ignorant of how the term is used for a flash process node.

How many layers are needed for each physical cell? Is it 1,2, or a lot more? Is this effectively 321 physical TLC cells stacked vertically and some planar style logic at the bottom of the stack.

Also, where do multiple pieces of silicon factor into this - I assume we might be up to 16 silicon dies deep with through-silicon-vias, which would mean a cross section of a package could actually have 5000 layers - that sounds crazy!