The website claims hardware acceleration and... I doubt they got timing closure on the soft CPU at anything greater than 100MHz and you still have to get data to/from it at likely 30~40 MB/s via an SDMMC bus.
The website claims hardware acceleration and... I doubt they got timing closure on the soft CPU at anything greater than 100MHz and you still have to get data to/from it at likely 30~40 MB/s via an SDMMC bus.
I switched a design from iCE40 to ECP5 and got a ~3x speedup "for free"
Agreed that using Lattice FPGAs is super nice, mostly because you get to use the open-source Yosys toolchain, which is vastly better than proprietary toolchains IMO
A quick search shows Hirose has a 0.5mm tall FPC connector that could fit 25 contacts within the width. Looking at their pictures, they have some spare height (unsure if enough though) and depth to move components forward. Even with good grounding, idk 12 IO is a decent amount.