Hacker News Reader

Comment by wtallis | Hacker News Reader

Video encode and decode aren't really GPU functions. They're totally separate IP blocks from the 3D graphics/vector compute part of the GPU. On Intel's previous laptop processor generation (Meteor Lake), the video encode and decode blocks were on an entirely different piece of silicon from the GPU.

View on HN

True. The display controller is also a different block, separated from the GPU and from the video codecs.

While on Lunar Lake the GPU and the video codec block are on the same tile, they are still in different locations on the compute tile.

In the new Arrow Lake S desktop CPU, to be announced tomorrow, the GPU is extracted on a separate tile, like in Meteor Lake, while the other two blocks related to video output, i.e. the video codec block and the display controller block, are located on a tile that contains the memory controller and a part of the peripheral interfaces and which is made using a lower-resolution TSMC process than the CPU and GPU tiles.

Benchmarking hardware encode is also a pretty specialized rabbit hole since it's not just the performance that varies, but also the quality of the results.

> the video encode and decode blocks were on an entirely different piece of silicon from the GPU.

As far as I understand this is not true. It's a different engine within the graphics device, and it shares the execution units.

For Meteor Lake, Intel provided slides to the press that clearly labeled media blocks on the SoC tile, not the GPU tile. The hardware encode and decode also definitely does not use the shader execution units.

AFAIK the video encode/decode pipeline is separate from the graphics pipeline. But they do reside on the graphics tile.

Reply on news.ycombinator.com