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Comment by johndoe0815 | Hacker News Reader

This is the RISC-V core used in the RP2350, the new Raspberry Pico 2 SoC.

Fun fact: to save space in the RP2350s ROM it contains a minimal ARM emulator for RISC-V, so that it can (mostly) use the same boot code for both architectures.

https://github.com/raspberrypi/pico-bootrom-rp2350?tab=readm...

https://github.com/raspberrypi/armulet

Just to clarify

> so ARM code is emulated (varmulet) on RISC-V

As I initially read this the other way around.

Ah, I read the rumor that there was an ARM emulator but didn't think it was open sourced. Thanks, that'll be a great example for my students...

It's also an interesting juxtaposition, because it directly allows to benchmark the architectures in the same system environment.

In the RP2350 it is possible to either use the RISC-V cores, the CM33 cores or even use one of each.

But such benchmarks don't tell you anything at all about general ARM vs RISC-V performance.

Those benchmarks would only tell you about those exact two cores, Cortex-M33 vs Hazard3. There are many other ARM and RISC-V implementations that are better and worse, depending on what customers need.

I dunno if it will be that interesting due to area differences. Maybe if Raspberry publish the area stats too?

They mentioned somewhere that they could not designate the actual area increase since it is part of the synthesized digital area. The area increase to include the RISC-V cores was negligible, apparently.

I wonder if without the RISC-V cores the design was pad limited i.e. it had due area that wasn't used. So, they put in the RISC-V cores for no die cost. There will be some cost to test the RISC-V cores.

Is a RISC-V core just the serial numbers filed off an ARM core?

The core design isn't tightly coupled to the front-end ISA. AMD zen was going fo be offered in both x86 and ARM but the ARM front-end was canceled.

No support for floating point. It would have been nice to have that.

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