That's not a guarantee. On some systems memory protection can be sub-page (not sure about x86).
But it sounds like the masking feature mentioned in a sibling comment takes care of it anyway.
But it sounds like the masking feature mentioned in a sibling comment takes care of it anyway.
It might not be the nicest thing to assume to be the case on all hardware, but it shouldn't be too unreasonable to put it under an "if (arch_has_a_minimum_page_size)". So many things already assume at least 4KB pages, Intel/AMD aren't gonna break like half the world. If anything, they'd want to make larger pages to make larger L1 caches more feasible.
I definitely see the conundrum since the dangerous code is such a huge performance gain.