Leading edge nodes are basically black magic and are right on the edge of working vs producing broken chips.
You as a customer would never want to be in a position where you are solely responsible for yields.
Nobody wants to give away trade secrets, so everything remains proprietary and behind an NDA until it has become completely obsolete.
[0]: https://www.skywatertechnology.com/sky130-open-source-pdk/
If you haven't watched this video, I highly recommend it: Indistinguishable From Magic: Manufacturing Modern Computer Chips https://www.youtube.com/watch?v=NGFhc8R_uO4 It's a little outdated now, but very comprehensive and gives you an idea of how totally nuts the chip business is.
NB: this is obviously a simplified explanation.
https://www.epfl.ch/research/facilities/cmi/equipment/photol...
1: https://semiengineering.com/knowledge_centers/materials/fill...
As an aside, few analog layouts will use the "line of diffusion" style that's common in the standard cells. And in analog one can find more exotic transistor patterns, like waffle [1], that aren't used in digital. Many things are possible, but it has to pass DRC.
[1] https://www.radioeng.cz/fulltexts/2019/19_03_0598_0609.pdf
What I can imagine, is that the foundry only tests their magic OPC algorithm with DRC clean inputs. If your mask isn't DRC clean, who knows what's coming out the other side.
You can't build a high-end fab for a couple of billion dollars.