Good for tessellation only if chips are also hexagons. Arguably chips themselves could be hexagons for better pin density and potentially thermal properties. Surprised nobody has tried this before.
When silicon area is expensive and performance can be maximised by reducing average on-die wire length, hexagons sound like they might make sense.
Obviously current layout tools prefer X-Y area splits, so a lot of tooling would have to be redesigned to make use of a probably rather small performance gain.
Wouldn’t they contaminate the just fabbed silicon surfaces? (That being said i have no idea how swarf is typically managed in die cutting.)
But it breaks too much of the existing flow to be worthwhile