Scientists find security risk in RISC-V open-source chip architecture
scmp.com
scmp.com
Assuming they really found a problem, it's in just one RISC-V core design, a student project, which is not used commercially -- at least directly: one of the original BOOM designers used it as the basis for the ET-Maxion core at Esperanto. It may be that some Chinese organizations have picked it up too.
Regardless, it is not an issue with the RISC-V specification.
Mate. You reference some random unspecified articles on the internet. The internet has thigs of widely varying quality and accuracy. If they are claiming to know e.g. what Apple's contract terms are with Arm then they almost certainly don't have any actual information. > I did some more reading last night.
Great nice. I'm glad you're researching RISC-V. Welcome aboard.
I've been heavily involved in RISC-V since late 2016 when I bought my first board. In 2017 I co-authored a conference paper ...
These are all just patronizing/backhanded ad hominems, and have nothing to do with the question that I was asking about and disagreeing with you on. The use of personal ad hominems in response to all the argumentative points I offered here: (https://news.ycombinator.com/item?id=39752900) is the sort of bad online behavior that kills rational discussion. Someone with your quantity of experience should know that.
Why not reply there?
By instead replying here, it looks like you're stalking/harassing a user across threads.
It is not a good look.
This is a bug in a student-built microarchitecture, not an issue with the ISA.