No, it's not even related to gate length or any kind of physical feature anymore. It's a purely marketing term. A "3 nm" node has a gate length around 16-18 nm.
We could just divide total gates by surface area for the chip, but that would confuse the process efficiency with the implementation details and then we sacrifice instructions per second for a marketing number.
mm² is perfectly adequate for what we are after.
"how large a planar FET should be for the transistor density used in this process"
Is this the case, I'm not entirely sure. If it is, there be a better unit for this measurement, absolutely.
PLANETS: PLANar Equivalent Transistor Size
Or hire a marketing team to figure a good one.