TSMC unveils 1.6nm process technology with backside power delivery

Ackshually, EUV was cracked by Sandia Labs research in the US, with EUV light sources built by Cymer in the US. ASML was the only one allowed to license the tech and integrate it into their steppers after they bough Cymer in 2013. Hence why US has veto rights to whom Dutch based ASML can sell their EUV steppers to, as in not to China, despite ow much ASML shareholders would like that extra Chinese money.

ps. Intel used to own 15% of ASML in 2012, now they own less than 2%.

If Intel pulls off DSA, they will be using a newer generation of technology compared to TSMC using an optimized older generation. Could TSMC still make better chips? Maybe. But Intel will likely be better.

Very interesting document - lots of numbers in there for real feature sizes that I had not seen before (Table LITH-1).

And this snippet was particularly striking:

Chip making in Taiwan already uses as much as 10% of the island’s electricity.

Earlier it was AMD. The most prominent era since their Athlon XP CPUs turned out to be noticeably more performant per GHz than Intel in 2001.

incidentally, this is the measure rest of the world is advertising, except usually in liters per 100km.

there's a good reason for this: comparisons linear instead of inversely proportional. 6l/100km is 50% better than 9l/100km. 30mpg vs 20mpg is... not as simple.

I guess it's a matter of approach. Europeans are traveling familiar, constant distances and worry about fuel cost. Americans just fill up their tank and worry how far they can go :)

Chip frequencies stagnated (end of Dennard scaling if I remember correctly) giving the impression that single threaded performance had stagnated, but since then chip makers have used increasing data and instruction parallelism to squeeze even more apparent single threaded performance out of chips. A 3ghz chip today is usually way faster on average code than a 3ghz chip 15 years ago. They also started expanding into multiple cores and adding more cache of course.

For fab processes we should just switch to transistor density. That still wouldn't capture everything (e.g. power efficiency) but would be a lot better than not-actually-nanometers.

For performance we really don't have a good single metric anymore since all these performance hacks mean different levels of gain on different code.

http://dataphys.org/list/grace-hopper-nanoseconds/

and the field of play here isn't 1D linear .. it's somewhere sort of a bit slightly > 2D (elements can be stacked, there are limitations on how much and how close)

It's the same situation as when AMD started putting numbers in their Athlon XP SKUs to tell "this CPU performs just as good as intel of that frequency".

I, for one, think it makes sense. Because as I consumer I don't care about actual transited length or density, all I care about is: performance, efficiency, price. I can assume that going from TSMC N5 to TSMC N3 would result in an increase in efficiency and performance.

People that do care about those things (i.e. electrical engineers) most likely don't use marketing materials...

The nm has always been a very rough approximate proxy for transistor density. Nothing has really changed about how what the number implies.

I find it so weird how so many people on hacker is so hung up on the “nm” numbering. None of these people are designing standard cell libraries and those that actually design standard cell libraries never cared about what’s in the marketing material anyway.

Lowe number means higher transistor density in some ways, on some parts of the chip. That’s all

Not saying TSMC won't, but they have so much more experience in the cutting edge.

"Well, yes, we're behind TSMC in technology, but in our dreams we're way ahead!"

btw, you appear to be shadow banned, probably on account of being downvoted for making short comments like "good" or "I don't get it"

Short & simple responses may be adequate at times, but usually people will view it as not adding anything

Perhaps reviewing guidelines https://news.ycombinator.com/newsguidelines.html will give an idea of the ideal being yearned for (granted, it's an ideal). In general, trying to enhance the conversation with relevant information/ideas. "your links are 404" was definitely relevant here

However, something like an 80286 didn't even require a heatsink, while my 80486 had a dinky heat sink similar to what you might find on a modern motherboard chipset. At the same time, on a micron node, wires were huge. A few special cases aside (DEC Alpha comes to mind), power distribution didn't require anything special beyond what you'd see on your signal wires, and wasn't a major part of the interconnect space.

Mapping out to 2024:

1) Signal wires became smaller than ever.

2) Power density is higher than ever, requiring bigger power wires.

So there is a growing disparity between the needs of the two.

At the same time, there is continued progress in figuring out how to make through-wafer vias more practical (see https://en.wikipedia.org/wiki/Three-dimensional_integrated_c...).

I suspect in 2000, this would have been basically restricted to $$$$ military-grade special processes and similar types of very expensive applications. In 2024, this can be practically done for consumer devices. As costs go down, and utility goes up, at some point, the two cross, leading to practical devices.

I suspect a lot of this is driven by progress in imagers. There, the gains are huge. You want a top wafer which is as close as possible to 100% sensor, but you need non-sensor area if you want any kind of realtime processing, full frame readout (e.g. avoiding rolling shutter), or rapid readout (e.g. high framerate). The first time I saw 3D IC technology in mainstream consumer use were prosumer-/professional-grade Sony cameras.

I have strong fundamentals, but again, I stopped following this closely maybe 15 years ago, so much of the above is speculative.

"Better" is relative, the layout introduces more fabrication steps so it's only better if you actually get some benefit from it. Decades ago designs didn't require as much power or have as many transistors to wire so it wasn't an issue.

You might as well ask why, since we can do it now, Shockley didn't simply start at 3nm. It's all a very long road of individual process techniques.

> You need very tiny wires through very tiny holes in locations very precisely aligned on both sides.

Key word here is "both sides". It has challenges similar to solder reflow on double sided boards: you need to ensure that work done on the first side isn't ruined/ruining work on the second side.

https://semiwiki.com/semiconductor-services/techinsights/288... seems to be a good description.

"The challenges with BPR are that you need a low resistance and reliable metal line that does not contaminate the Front End Of Line (FEOL). BPR is inserted early in the process flow and must stand up to all the heat of the device formation steps."

Contamination = metals used musn't "poison" the front-side chemistry. So they end up using tungsten rather than the more usual aluminium. (Copper is forbidden for similar chemistry reasons)

It also (obviously) adds a bunch of processing steps, each of which adds to the cost, more so than putting the rails on the front side.

Historically, everything was etched, grown, deposited, and sputtered on one side of the wafer. The rest of the wafer was mostly mechanical support. The other side of the wafer is a universe away.

The world is more complex today, but that's a good model to keep in mind.

For a 3d integrated circuit, you would do this, and then e.g. grind away the whole wafer, and be left with a few micron thick sheet of just the electronics, which you'd mechanically place on top of another similar sheet. That's every bit as complex as it sounds. That's why this was restricted to very high-end applications.

As for whether the wafer is a huge ground plane, that's complex too, since it depends on the top of the device and the IC:

* First, it's worth remembering a pure silicon crystal is an insulator. It's only when you dope it that it becomes a conductor. The wafer starts out undoped.

* Early ICs had the whole wafer doped, and the collector of all the NPN transistors was just the wafer. There, it was a ground plane.

* SOI processes deposit a layer of glass on top of the wafer, and everything else on the glass. There, the wafer is insulated from the circuit.

So all of this can very quickly go in many directions, depending on generation of technology and application.

I'm not sure this post is helpful, since it's a lot of complexity in an ELI5, so I'll do a TL;DR: It's complicated. (or: Ask your dad)

Shorting is for only the most incontrovertible frauds as far as I'm concerned.