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Comment by usmannk | Hacker News Reader

why does the hardware addressability reasoning hold for RAM but not SSDs?

NAND flash is... weird. The old generation of SLC and MLC flash actually had more than the binary size, with the extra being used for error correction and wear leveling information. Newer MLC has larger "spare area", but is sufficiently unreliable that SSDs tend to round down the binary size to a decimal number and use the difference for replacing bad blocks as they wear out and fail.

TLC flash has a capacity that's actually a multiple of 3 times a power of 2, with an additional spare area. I believe a "128GB" TLC SSD might have somewhere around 150GB of writable bits.

Your computer does not have a problem with non-existing LBAs. The SSD controller might not like missing raw flash addresses, but that's abstracted away from the user perspective anyway, even if for no other reason than the FTL.

But spinning hard drive and SSDs are not working at the byte level, but at a power of two block. 512B to 4kiB usually.

You purchase a number of those blocks, and the total amount of byte is a power of two.

The filesystem then stores everything in it's own blocks, composed of one or more disk/SSD blocks.

Files on disk therefore consume a number of blocks, making their storage usage a power of two (the real size can by anything of course).

And you might as well align blocks to memory pages when buffering/reading/writing the filesystem. Since you must align memory access for performances with CPU cache, RAM is loaded/stored itself in blocks of 256 or 512 bits those days (yes reading one byte from RAM will rapatriate that much) etc.

That's a lot of power or two (you could argue power of 12 [4kiB]) designed everywhere.

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