Oh man, this brings me back nearly 25 years from today. I was doing some undergrad EE coursework at Cornell, and took a few classes taught by Rajit Manohar; he had also been a part of the async scene at Caltech (though after Alain Martin's original work, I believe he published with Martin later). Thought it was really interesting, and part of the coursework involved coming up with some small, toy async chip designs. I remember CSP/CHP all too well; at first I just didn't get it, but one day it just kinda clicked with me and I became pretty decent at writing out my logic in CHP.

Async designs never really went anywhere for general-purpose computing, but I always thought it was a cool way of approaching the problem, especially from a power-consumption perspective. Even all the adaptive clock rate stuff in modern CPUs doesn't quite do what those async chips could.

Edit: oh wow, I actually just found some of my old coursework files from ECE574 from the spring of 2002, complete with some CHP that I no longer understand at all. Unfortunately couldn't find any sort of project website that Rajit may have left up (like he did for the VLSI intro course of his I'd taken the prior semester).