25 Years Ago: The First Asynchronous Microprocessor (2014)

Async processors have been around a long time, and some were sold commercially in the pre-microprocessor days. The IAS machine and clones, designed by von Neumann's team in the 1940s, was asynchronous. A bit later, the PDP-6 and first generation of PDP-10, were too, as well as Honeywell's mainframe processors in the 70s and 80s:

> The 6180 processor was among the last of the great non-microcoded engines. Entirely asynchronous, its hundred-odd boards would send out requests, earmark the results for somebody else, swipe somebody else's signals or data, and backstab each other in all sorts of amusing ways which occasionally failed (the "op not complete" timer would go off and cause a fault). Unlike the PDP-10, there was no hint of an organized synchronization strategy: various "it's ready now", "ok, go", "take a cycle" pulses merely surged through the vast backpanel ANDed with appropriate state and goosed the next guy down. Not without its charms, this seemingly ad-hoc technology facilitated a substantial degree of overlap [...] [1]

I think it's fair to say it's harder to reason about async logic. And nearly all design tools are today oriented around clocked logic. So asynchronous designs have become very niche (and they were never mainstream). But the basic premise that it is more efficient, is probably true.

[1] https://www.multicians.org/mga.html#6180

Oh man, this brings me back nearly 25 years from today. I was doing some undergrad EE coursework at Cornell, and took a few classes taught by Rajit Manohar; he had also been a part of the async scene at Caltech (though after Alain Martin's original work, I believe he published with Martin later). Thought it was really interesting, and part of the coursework involved coming up with some small, toy async chip designs. I remember CSP/CHP all too well; at first I just didn't get it, but one day it just kinda clicked with me and I became pretty decent at writing out my logic in CHP.

Async designs never really went anywhere for general-purpose computing, but I always thought it was a cool way of approaching the problem, especially from a power-consumption perspective. Even all the adaptive clock rate stuff in modern CPUs doesn't quite do what those async chips could.

Edit: oh wow, I actually just found some of my old coursework files from ECE574 from the spring of 2002, complete with some CHP that I no longer understand at all. Unfortunately couldn't find any sort of project website that Rajit may have left up (like he did for the VLSI intro course of his I'd taken the prior semester).

There have been other successes since, perhaps most famously Fulcrum (acquired my Intel in 2019) with their fully asynchronous networking switches.

ADD: another impressive result was Ivan Sutherland's (yes, that Ivan Sutherland) crazy fast 8x8 cross bar. He's still active in the topic: https://arc.cecs.pdx.edu/publications/

> the frequency goes from 3Hz at 0.4V to 680KHz at 1.1V

now _that's_ underclocking :)

"As the technology finally reaches industry"

Have I missed some news?

If I remember, one promising aspect of the tech was that different subsystems could effectively run at different speeds, and could therefore be developed independently of the rest of the design.

It might pair well with TTA cpu designs, which I think Ivan Sutherland was also involved in.

How does this compare to:

https://en.wikipedia.org/wiki/AMULET_(processor)