The primary point of CML is that a differential signal is interference resistant. Therefore it can be used for higher data rates in out-of-chip buses. It does not provider faster ALUs than CMOS.
CMOS logic can also be differentially routed, and often is routed against interference. That + a full shield around sensitive routing like clock lines are standard practice. Both have the advantage of cobtaining the return current too.
I'm not suggesting we switch to 3 wires for ternary. That would be stupid. Ternary CML is 2 wires. 10, 00, 01 with 11 being the forbidden state or having the same functionality of 00. This isn't efficient from routing perspective compared to single-ended CMOS.
For large routing distances any kind of encoding can be used. I often use 2 dimensional (row-column) encoding/decoding for multi-GHz data busses travelling over long distances (like 500um to couple of mm). It's very easy to calculate the power cost and routing area cost of not using any emcoding with respect to doing an n-dimensional encoding (incl. the power and area of encoder/decoder). I even used a 3D encoding which reduced total routing channel area and power in a routing dense setup like 50%. Using a simple kind of coding like parity bit and multiplying the data with a random sequence is also used against interference but people often don't do this and regret it..
Anyhow, the point I'm trying to make is local logic and long distance routing are two problems with different optimization parameters.