Well, the way we use CMOS logic is like this. But we have a bunch of other logic families inplemented with MOSFETs. Dynamic logic is seldom complementary. CML too. There's no reason to not have 3-state CML.

Ternary logic is used in data converters (Analog-to-digital and digital-to-analog) with succes. This is because these circuits are often differential, so for each 1 there is a -1 on the complementary side. Let's say it's a current steering DAC. For 1 the positive end will sink +1 unit current while negative end is sourcing +1 (effectively -1). We get -1 if we flip the positive and negative. 0 can be created by turning off the currents. The beauty of it is the 3-levels we created are inherently linear, which doesn't extend to higher bases! The DAC unit in this example is in logic terms a CML ternary inverter! It doesn't consume any power when in 0 state, so it improves CML power cobsumption too (>50% for uniform data activity).

Now we established that it is possible to implement ternary logic: why is it not used? Because CMOS logic only consumes power during transition (dynamic power) while CML consumes quite a bit higher static power always. Actually CML can work at much higher speeds but it's gobe out of fashion because Moore's law till recently gave more transistors in the same area operating faster than the previous generation. When the Moore's law is died a slow death we went for increasing the die sizes by doing more in parallel than faster logic, because for complicated reasons CMOS is quite efficient when operating much slower than the speed limits of technology. This being said, there might be areas CMOS logic can be replaced but people don't do it because they don't think about the possibility. At least this is my observation in the field.