Like how the Transmeta Crusoe was an x86-compatible CPU... but moreso.
The Crusoe was a thing marketed as a "CPU", that was actually internally an SoC (with the CPU inside it being non-x86.) This SoC had its own internal RAM and storage, and booted itself into internal software that then emulated an x86 CPU. All of the "CPU" data pins on the Crusoe SoC, routed to the virtual CPU inputs and outputs of this software. So, as far as other devices in the system were concerned, they were speaking to an x86 CPU.
Did anyone ever try taking this concept further? Maybe in the context of an industrial embedded computer?
I could imagine someone taking e.g. a modern ARM SoC with onboard RAM + eMMC; setting it up to boot into e.g. Bochs to emulate a virtual x86 (CPU + BIOS + other memory-mapped ROMs + platform controller hub + IO controllers + timer chips + TPM + etc — all the stuff on an x86 motherboard) — and then just setting up the SoC's GPIO pins to directly expose all the virtual buses of that virtual motherboard. You could then take such a chip, and design a physical "motherboard" for it to sit in, that's just a bunch of ports (e.g. PS2) and slots (e.g. ISA or maybe very slow PCI) routing directly to the SoC's GPIO pins.
This would be a very effective strategy, I think, for producing low-cost host platforms for the many industrial-automation ISA cards that still exist. So I have a feeling some OEM has at least tried to do this.
Probably there wouldn't be enough GPIO pins for most busses — x86 CPUs have tons of pins compared to almost any other architecture. So I wouldn't consider it cheating to feed parallel busses out serially at higher clock rates than those busses natively run at, and then to require the use of an external ser/des chip or two to flatten the signals back out. As long as it's the SoC itself speaking the protocol and the chip is "dumb", I think that'd still count.
Also keep in mind that unlike with the Crusoe, an "x86-on-ARM SoC" wouldn't need to have GPIO fast and wide enough to talk to external DRAM — as any memory could be internal to the SoC without breaking the contract. So the main constraint bottlenecking the Crusoe's CPU performance, wouldn't apply here. This thing could actually perform decently well — possibly well enough to run hard-realtime industrial control software coded in the 1990s, and to speak to ISA cards built in the 1990s. Which is all it would need to be able to do, for the obvious use-case.