I guess this is a process limitation? i.e, the stuff you would need to make an appropriate step down isn't compatible with the other stuff they need?
1. Process limitations (no high voltage devices, poor analog characteristics, limited resistor choice, etc)
2. The skill set for power device/analog IC design is very different than digital design (and harder to recruit for as the talent base is relatively small).
3. On chip power converters universally suffer from poor inductor quality which trashes your efficiency (thus increasing cooling demands as well).
From a business perspective it would be quite risky and likely not cost effective.
As for skillset, there are a bunch of IP companies with silicon proven designs available. I'm sure they didn't design their SERDES or PLL(s) in-house either.
They also have another design advantage here. I believe they're not IO limited with their bumps.So they can use most of it for power, which is much better than any DC-DC solution.