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Comment by vpribish | Hacker News Reader

20,000 Amps has to be a mis-statement. or there's some qualifier they are not mentioning. it doesn't look like an industrial arc-furnace

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It's not. The CS-2 they claim can do 23kW peak. The voltage is very low. If 23kW and 20kA is right, it's a 1.15V core voltage, which is pretty normal these days.

For comparison, one of the workstation AMD EPYC processors uses ~400W under peak load, and would use approximately ~320A peak current. It's only ~30x more current... modern CPUs use an enormous amount of current these days.

They mention that the CS-2 runs at very low, efficient clocks compared to a CPU or GPU. So yeah, the voltage should be quite low.

1.15V is quite high for the core voltage of a modern efficiency-focused CPU. A lot of them are around 0.7-0.9V by comparison.

1.15V isn't that high. Most CPUs may idle at ~0.9V but when running full power, they throttle up much higher. Overclocking the modern Ryzen 7000 series seems to top out at ~1.2V. If this giant wafer isn't on the absolute latest process, that voltage is going to go up. So, 1.15V seems very reasonable to me.

850k cores apparently.

We have EPYC chips with ~100 cores at ~200w TDP. So each core is around 2W in the AMD chips. Core voltages are ~1v with modern CPUs. So that's 2A per core.

850k cores at 20kA is very much lower than the AMD chips. Must be massively parallel, lower-performing cores. But it's quite feasible that it needs 20kA.

The CS-2 system on their website specs out at 23kW peak. So all this lines up with each other.

As far as benchmarks and utility of such systems, I am not sure if they've proven it out.

What is interesting to me is that it was easier to sling 20kA round the chip than to make a higher voltage power distribution bus and step down nearer the cores.

I guess this is a process limitation? i.e, the stuff you would need to make an appropriate step down isn't compatible with the other stuff they need?

Couple of likely reasons:

1. Process limitations (no high voltage devices, poor analog characteristics, limited resistor choice, etc)

2. The skill set for power device/analog IC design is very different than digital design (and harder to recruit for as the talent base is relatively small).

3. On chip power converters universally suffer from poor inductor quality which trashes your efficiency (thus increasing cooling demands as well).

From a business perspective it would be quite risky and likely not cost effective.

TSMC 7nm has all the required stuff to build a DC-DC converter from 3V or 1.8V. Nobody would use on-chip inductors for high power DC-DC.

As for skillset, there are a bunch of IP companies with silicon proven designs available. I'm sure they didn't design their SERDES or PLL(s) in-house either.

Efficient DC-DC converters are area consuming due to high voltage devices abd the capacitors in general being very large. You would need SMD inductors on top of that. This means you used very precious silicon area for power delivery. It creates a lot of reliability headache since higher voltages cannot be routed closer to low-voltage stuff. If you're not crazy high in current consumption density (A/mm2) it doesn't make sense.

They also have another design advantage here. I believe they're not IO limited with their bumps.So they can use most of it for power, which is much better than any DC-DC solution.

The low voltage power rails on consumer Ryzen and Intel chips exceed 100 amps.

My desktop CPU uses 200 Amps. At 1v.

She definitely says "the way we bring 20,000 amps into the front side of the wafer" (around 2'17'' into the video). It does seem an awful lot.

Core voltage is going to be in the ballpark of 1V, and given the stated power consumption is 15kw that means a minimum of 15kA. So, it is indeed a lot but the math checks out.

how much of that power actually reaches the chip though? (it's hilarious that this is one chip)? this thing is mostly a water pump - I just can't - everything about it is just wild

Most of it. The water pump and other stuff consumes probably less than 500W total. There's some efficiency loss in the actual power converters, but they're likely designed to be >95% efficient (probably >98%), otherwise cooling them would be a nightmare.

7nm core voltage is 0.75V. If they want good reliability, 0.7V underdrive is understandable. So, 2.2kA at 0.7V sounds reasonable to me.

This pdf (https://f.hubspotusercontent30.net/hubfs/8968533/CS-2%20Data...) says the power supplies are 6+6 redundant 4kW supplies. Assuming 100% utilization (not realistic, but it makes the "math" easy) that's 24kW of "power supply".

If we presume the wafer consumes a large percentage of that (say 20kW out of the 24kW max) and that they are feeding the "wafer" with DC at 1v, then they /do/ need to feed in 20,000 amps to deliver 20kW of power at 1v.

So yes, 20kamp is a lot of current, but it is within the "power budget" the device seems to express in its marketing material.

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